1. Field of Invention
The present invention relates to a method of using an NROM. More particularly, the present invention relates to a method of controlling a multi-state NROM.
2. Description of Related Art
FIG. 1 is a schematic cross-sectional view of a conventional flash memory cell. As shown in FIG. 1, the flash memory cell includes a gate electrode that consists of a floating gate 12 and a control gate 14. The floating gate 12 is a polysilicon layer for holding electric charges. The floating gate 12 is always in a `floating` state because the gate 12 is disconnected from external circuits. The control gate 14 is used for controlling data access. Each memory cell is capable of holding a single bit. In other words, each memory cell can only distinguish between logic states `0` and `1`. FIG. 2 is a simple graph showing the conventional method of distinguishing between logic `1` and `0` in a memory cell. As shown in FIG. 2, a voltage Vread is applied to the gate when data access is required. If the threshold voltage of the memory cell is smaller than Vread (for example, Vt1), a large current is sensed implying a logic state `1`. On the other hand, if the threshold voltage of the memory cell is greater than Vread (for example, Vt2), very small current is detected implying a logic state `0`.
Following the introduction of high-density flash memory, memory capable of distinguishing a multiple of state is developed. FIG. 3 is a graph showing a conventional method of distinguishing four different states in a memory cell (including `00`, `01`, `10` and `11`). As shown in FIG. 3, three standard reading voltages Vr1, Vr2 and Vr3 are set to distinguish between four different types of threshold voltages (Vt1, Vt2, Vt3 and Vt4). However, threshold voltage region cannot be made very large because Fowler-Nordeim (F-N) tunneling current is easily affected by any deviation in the processing parameters such as the variation of tunneling oxide thickness and the variation of tunneling junction area. The deviation of such F-N tunneling current often affects the size of threshold voltage region for accessing data inside a memory cell array. Together with dimensional limitations of a chip, most flash memory cell can only support two storage states. Hence, a higher memory storage capacity is difficult to attain.
On the other hand, an NROM memory cell is able to hold a data bit in the drain terminal and the source terminal. However, the drain terminal and the source terminal need to be connected in reverse during programming and reading, leading to the need for quite complicated control circuits. Moreover, if a neighboring bit undergoes some programming when current is being measured, the so-called second-bit effect may occur leading to a considerable reduction of the original high current. In addition, since both terminals are employed to hold data, scaling down is made more difficult.